The prior art is replete with nonvolatile memory storage devices. One type is EEPROM (electrically erasable programmable read-only memory), which is user-modifiable read-only memory (ROM) that can be erased and reprogrammed multiple times through the application of higher than normal electrical voltage. One disadvantage of an EEPROM chip, however, is that it has to be erased and reprogrammed in its entirety, not selectively. Another disadvantage is its limited life. More particularly, the number of times it can be reprogrammed is limited to tens or hundreds of thousands of times.
A special form of EEPROM is flash memory, which uses normal PC voltages for erasure and reprogramming. Flash memory, or flash RAM, is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. It is a variation of EEPROM which, unlike flash memory, can be erased and rewritten at the byte level, which is slower than flash memory updating. When flash memory needs to be rewritten, the flash memory can be written to in block (rather than byte) sizes, making it easy to update.
Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or “flash.” The erasure is caused by Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove an electronic charge from a floating gate associated with each memory cell. FIG. 1A is a graph 10 illustrating the association of voltage with a binary state for a prior art Flash EEPROM cell having an offset gate. As shown, if the voltage is above 6.5 V, the cell is storing a 0. If the voltage is below 3.5 V, the cell is storing a 1. FIG. 1B is a graph 12 illustrating the association of voltage with a binary state for a prior art Flash EEPROM cell having a self aligned gate.
FIG. 1C is a graph 14 illustrating the association of voltage with a binary state for a prior art NAND EEPROM cell.
MRAM (magnetoresistive random access memory) is a method of storing data bits using magnetic charges instead of the electrical charges used by DRAM (dynamic random access memory). Scientists define a metal as magnetoresistive if it shows a slight change in electrical resistance when placed in a magnetic field.
Conventional random access memory (RAM) computer chips store information as long as electricity flows through them. Once power is turned off, the information is lost unless it has been copied to a hard drive or floppy disk. MRAM, however, retains data after a power supply is cut off. It would be desirable to generate a type of MRAM based on spin electronics, the science behind giant magnetoresistive heads used in disk drives.
One prior art spin-valve type memory device is disclosed in commonly assigned U.S. Pat. No. 5,343,422. In FIGS. 2A and 2B, storage element 20 embodying the invention comprises a suitable substrate 22, such as glass, ceramic or a semiconductor, upon which are deposited a first thin film layer 24 of soft ferromagnetic material, a thin film layer 26 of a nonmagnetic metallic conducting material such as copper, and a second thin film layer 28 of ferromagnetic material.
Note that the storage element 20 is rectangular, and that the easy axis of magnetization is along the length of the storage element. The magnetization direction of magnetic layer 28 is fixed (see arrow 29) to be parallel to the longitudinal dimension of the storage element, such as by exchange coupling with an antiferromagnetic layer 30. However, if preferred, the layer 30 may be eliminated provided layer 28 is of a sufficiently hard magnetic material or has sufficiently high anisotropy to retain its magnetization during state switching operations.
The magnetization of layer 24 is constrained by the uniaxial anisotropy and the shape geometry to lay in the longitudinal direction of element 20, either parallel (see arrow 31, FIG. 2A) or antiparallel (see arrow 33, FIG. 2B) to the fixed direction of magnetization of the layer 28. Switching of the storage element 20 between the “1” state (FIG. 2A) and the “0” state (FIG. 2B) is accomplished by simultaneously applying a transverse field and a longitudinal field to element 20. The longitudinal field is induced by a longitudinal write current 32 in a write line 34 provided by a conductor that extends orthogonal to the length of the storage element 20. The transverse field is induced by a transverse write/sense current 36 flowing lengthwise through the element 20. If desired to increase stability by enhancing the transverse field, additional transverse write/sense current may be provided via an optional separate conductor 37 that extends lengthwise through the storage element and is interposed between substrate 22 and an insulating layer 38 that contacts layer 24, as shown only in FIG. 2A.
However, it would be desirable to allow reorientation of all pinned layers to allow the net magnetic moment of layers 24 and 28 to remain at ˜0 upon switching states. It would also be desirable to allow writing to the element 20 with a single write circuit rather than requiring multiple electrical circuits for each memory cell.